Course Title and Code: Microcomputer System Design, COE 305
Credits and contact hours: (4,6)
- Barry B. Brey, The Intel Microprocessors, Processor Architecture, Programming, and Interfacing, Seventh Edition, 2006, Prentice Hall
- other supplemental materials: Ramesh Gaonkar, Microprocessor Architecture, Programming, and Applications with 8085.
Specific course information
- Brief description of the content of the course (catalog description): Microprocessor architecture and organization, Bus architectures, types and buffering techniques, Memory and I/O subsystems, organization, timing and interfacing, Peripheral controllers and programming. The practice of the design of a microprocessor system design, testing, debugging and reporting.
- Prerequisites or co-requisites: Digital Logic Lab (COE 203) and Computer Organization and Assembly Language (COE 205)
Specific goals for the course
Specific outcomes of instruction: After successfully completing the course, students will be able to
- Describe the functions of various pins on the processor and processor Memory/IO Read and Write bus cycle operations.
- Identify the main types of memory technology, describe memory, internal organization and design an interface to memory.
- Specify and design simple computer serial and parallel interfaces.
- Describe how interrupts are used to implement I/O control and data transfers, design small interrupt service routines and I/O drivers using assembly language.
- Describe data access from magnetic and optical disk drives using DMA.
- Recognize various types of bus interfaces in a computer system.
- Design and fabricate a medium-sized 8086 based microcomputer system.
Explicitly indicate which of the student outcomes listed in Criterion-3 or any other outcomes are addressed by the course:
- Outcome 1: [Mapped from “c”]
- Outcome 2: [Mapped from “e”]
- Outcome 3: [Mapped from “l”]
Brief list of topics to be covered
- 8086 Processor Architecture: Processor Model, Programmer’s model, Designer's Model: 8086 hardware details, Clock generator 8284A, Bus buffering and latching, Processor Read & Write bus cycles, Ready and waitstate generation, Coprocessor NDP 8087 interface, 8288 bus controller, Pentium processor architecture.
- Memory Interfacing: 80x86 Processor-Memory interfacing, Address decoding techniques, Memory Devices – ROM, EPROM, SRAM, FLASH, DRAM devices, Memory internal organization, Memory read and write timing diagrams, DRAM Controller